Computer Architecture

One of the drivers of research in computer architecture is the desire to make efficient use of the computational power available. In early computers peripheral operations and transfers between main memory and backing storage took place under direct program control using instructions that required milliseconds for their completion. When the Manchester Atlas was being designed in the late 1950s, the disparity between processor and peripheral speeds was so great that it became clear that the processor would need to be able to switch rapidly between processes, thus leading to a multiprogramming system and the invention of virtual memory.

By the 1980s most high-performance processors were heavily pipelined and incorporated cache memory and branch outcome prediction mechanisms. This meant that discontinuities occured at much finer levels of granularity, with events such as cache misses or unpredicted branch outcomes causing long instruction latencies. This led to the use of a micromultiprogramming strategy in which a process switch was initiated whenever a latency-inducing operation was encountered. At Edinburgh Nigel Topham proposed the idea of a "context flow" architecture and led an examination of the design possibilities for uniprocessors and multiprocessors based on this concept. Details can be found in Volume 2 of the Journal of Supercomputing:

Consideration of the hardware required to support a shared memory multiprocessor implementation of the Context Flow architecture led to an investigation of processor-memory interconnection techniques. A common bus can work well for shared memory systems with a few tens of processors but for larger systems the simplest way to implement full connectivity between N processors and M memory units is to use a crossbar switch. However, the hardware cost, proportional to N x M, soon becomes prohibitive as N and M increase. Instead, in a system where M = N, an N x N crossbar switch can be implemented as a Benes network of two N/2 x N/2 crossbar switches. Each of these crossbars can be similarly reduced, allowing a network to be constructed entirely from 2-input, 2-output switch nodes arranged in layers and suitably connected, as shown in the figure below. Two example paths are shown, from input 7 to output 3 and from input 2 to output 1.

The demonstration silicon chip fabricated as part of the Xbar project was a 4 x 4 crossbar switch intended for use in a data-parallel packet-switched system, with one crossbar transmitting requests from a set of processors to a set of memories and one transmitting data from the memories to the processors. In either crossbar, requests could be made simultaneously from any number of inputs. This required a strategy to avoid packets being lost. To avoid this problem and to maximise throughput, the strategy chosen was to incorporate hardware queues into the chip. Details of the project can be found in a Computer Science Research report "Design of a bit-sliced network for a shared-memory multiprocessor system" (CSR-19-92).

A collaboration with Ken McKinnon in the Mathematics Department led to a project to investigate possible architectural mechanisms to support efficient processing of sparse vectors. Sparse vectors are an important feature of a number of computer applications, especially linear programming, a technique used commercially to optimise the outcome of a set of activities. Typically, only a small fraction of the elements of a sparse vector have non-zero values, so it is important to avoid wasting memory space and compute cycles dealing with the zero values. The list vector mechanism built into the design of the Edinburgh Sparse Processor (ESP) does just this and also solves the problem of fill-in. Fill-in occurs when the output from an operation on a sparse vector contains more non-zero values than it did previously. Details can be found in the Proceedings of the 16th annual International Symposium on Computer Architecture (ICSA '89)

Nigel Topham's experience in investigating a variety of architectural techniques led to his being invited to work as a processor designer with several industrial concerns including the Advanced Computer Research Institute (ACRI), a French supercomputing startup, Siroyan and ARC International plc. At ARC he led the design of the ARC-600 embedded processor, subsequently implemented widely in many billions of chips, the second most-widely used embedded processor architecture after ARM7.